Power estimation tool cadence

Cybersecurity Research Center Overview Research. Resources Events Webinars Newsletters Blogs. Comprehensive Software Analysis. Manage Business and Software Risk. All Synopsys. Adding a Verilog Blackbox Resource File 6. Defining a Chisel BlackBox 6. Defining a Chip with a BlackBox 6.

Software Testing 6. Memory Hierarchy 6. The L1 Caches 6. The System Bus 6. The SiFive L2 Cache 6. The Broadcast Hub 6. The Outer Memory System 6. Chipyard Boot Process 6. Adding a Firrtl Transform 6. Where to add transforms 6. Examples of transforms 6. IOBinders and HarnessBinders 6. IOBinders 6. HarnessBinders 7. Target Software 7. FireMarshal 7. Advanced Concepts 8. Tops, Test-Harnesses, and the Test-Driver 8. BaseSubsystem 8. Subsystem 8. System 8.

Tops 8. TestHarness 8. TestDriver 8. Communicating with the DUT 8. Debugging with JTAG 8. Example Test Chip Bringup Communication 8. Intro to Typical Chipyard Test Chip 8. Simulation Setup of the Example Test Chip 8. Debugging RTL 8. Waveforms 8. Print Output 8. Basic tests 8. Torture tests 8. Firesim Debugging 8. Debugging BOOM 8. Setting up Dromajo Co-simulation 8. Accessing Scala Resources 8. Context-Dependent-Environments 8.

Site 8. Here 8. Creating Clocks in the Test Harness 9. TileLink and Diplomacy Reference 9. TileLink Node Types 9. Client Node 9. Manager Node 9. Register Node 9. Identity Node 9. Adapter Node 9. Nexus Node 9. Diplomacy Connectors 9. TileLink Edge Object Methods 9. Get 9. Put 9. Arithmetic 9. Logical 9. Hint 9. AccessAck 9. HintAck 9. Register Router 9. Basic Usage 9. Decoupled Interfaces 9. Using Functions 9. Register Routers for Other Protocols 9.

Diplomatic Widgets 9. TLBuffer 9. AXI4Buffer 9. AXI4UserYanker 9. AXI4Deinterleaver 9. TLFragmenter 9. AXI4Fragmenter 9. TLSourceShrinker 9.

AXI4IdIndexer 9. TLWidthWidget 9. TLROM 9. Prototyping Flow General Setup and Usage Log in. Install the app.

Contact us. Close Menu. Welcome to EDAboard. To participate you need to register. Registration is free. Click here to register now. Register Log in. JavaScript is disabled. Before starting Cadence Innovus, we need to create two files which will be loaded into the tool. The first file is a. This file is where we specify our target clock period, but it is also where we could specify input or output delay constraints e.

Use Geany or your favorite text editor to create a file named constraints. In this case, we are targeting a MHz clock frequency i.

You should replace the target clock period with whatever clock period was used to successfully meet timing in the previous section. A corner is a characterization of the standard cell library and technology with specific assumptions about the process, temperature, and voltage PVT.

To ensure our design will work across a range of operating conditions, we need to evaluate our design across a range of corners. Use Geany or your favorite text editor to create a file named setup-timing. This file includes information about the resistance and capacitance of every metal layer.

In this specific example, we are creating a typical corner by putting together the typical. Now that we have created our constraints. As we enter commands we will be able use the GUI to see incremental progress towards a fully placed-and-routed design.

We need to set various variables before starting to work in Cadence Innovus. These variables tell Cadence Innovus the location of the MMMC file, the location of the Verilog gate-level netlist, the name of the top-level module in our design, the location of the.

The next step is to do some floorplaning. This is where we broadly organize the chip in terms of its overall dimensions and the placement of any previously designed blocks. For now we just do some very simple floorplanning using the floorPlan command. In this example, we have chosen the aspect ratio to be 1.

If the cell utilization is too high, Cadence Innovus will spend way too much time trying to optimize the design and will eventually simply give up. We have also added 4. The following screen capture illustrates what you should see: a square floorplan with rows where the standard cells will eventually be placed. The next step is to work on power routing.

Recall that each standard cell has internal M1 power and ground rails which will connect via abutment when the cells are placed into rows. If we were just to supply power to cells using these rails we would likely have large IR drop and the cells in the middle of the chip would effectively be operating at a much lower voltage.

During power routing, we create a grid of power and ground wires on the top metal layers and then connect this grid down to the M1 power rails in each row. We also create a power ring around the entire floorplan. Before doing the power routing, we need to use the globalNetCommand command to tell Cadence Innovus which nets are power and which nets are ground there are many possible names for power and ground! We now create a power ring around our chip using the addRing command.

A power ring ensures we can easily get power and ground to all standard cells. The command takes parameters specifying the width of each wire in the ring, the spacing between the two rings, and what metal layers to use for the ring.

These top layers have high capacitance but this is not an issue since the power and ground rails are not switching and indeed this extra capacitance can serve as a very modest amount of decoupling capacitance to smooth out time variations in the power supply. We have power and ground rails along each row of standard cells and a power ring, so now we need to hook these up.

We can use the addStripe command to draw wires and automatically insert vias whenever wires cross. The following screen capture illustrates what you should see: a power ring and grid on M6 and M7 connected to the horizontal power and ground rails on M1.

You can toggle the visibility of metal layers by using the panel on the right. Click the checkbox in the V column to toggle the visibility of the corresponding layer.

You can also simply use the number keys on your keyboard. Pressing the 6 key will toggle M6 and pressing the 7 key will toggle M7. Zoom in on a via and toggle the visibility of the metal layers to see how Cadence Innovus has automatically inserted a via stack that goes from M1 all the way up to M6 or M7. The following screen capture illustrates what you should see: the gates have been placed underneath a sea of wiring on the various metal layers.

Note that Cadence Innovus has only done a very preliminary routing, primarily to help improve placement. You can use the Amobea workspace to help visualize how modules are mapped across the chip. However, we recommend using the design browser to help visualize how modules are mapped across the chip. Here are the steps:. In this way you can view where various modules are located on the chip.

The following screen capture illustrates the location of the five MinMaxUnit modules. Notice how Cadence Innovus has grouped each module together. The placement algorithm tries to keep connected standard cells close together to minimize wiring.

The next step is to improve the quality of the clock tree routing. In the right panel click on Net and then deselect the checkbox in the V column next to Signal , Special Net , Power , and Ground so that only Clock is selected. You should be able to see the clock snaking around the chip connecting the clock port of all of the registers.

If you watch closely you should see a significant difference in the clock tree routing before and after optimization. The following screen capture illustrates the optimized clock tree routing. The routes are straighter, shorter, and well balanced. This will result in much lower clock skew. The next step is to improve the quality of the signal routing. Display just the signals but not the power and ground routing by clicking on the checkbox in the V column next to Signal in the left panel.

Then use the routeDesign command to optimize the signal routing. If you watch closely you should see a significant difference in the signal routing before and after optimization.

The following screen capture illustrates the optimized signal routing. Again the routes are straighter and shorter. This will reduce the interconnect resistance and capacitance and thus improve the delay and energy of our design. Filler cells are essentially empty standard cells whose sole purpose is to connect the wells across each standard cell row. Zoom in to see some of the detailed routing and take a moment to appreciate how much effort the tools have done for us automatically to synthesize, place, and route this design.

The following screen capture shows some of this detailed routing. Notice how each metal layer always goes in the same direction. So M2 is always vertical, M3 is always horizontal, M4 is always vertical, etc. This helps reduce capacitive coupling across layers and also simplifies the routing algorithm. This is an example of the sophisticated algorithms used in these tools. Our design is now on silicon! Obviously there are many more steps required before you can really tape out a chip.

For example, one thing we want to do is verify that the gate-level netlist matches what is really in the final layout.

We can do this using the verifyConnectivity command. Now we can generate various output files. We might want to save the final gate-level netlist for the chip, since Cadence Innovus will often insert new cells or change cells during its optimization passes.

We can also extract resistance and capacitance for the metal interconnect and write this to a special. You may get an error regarding open nets. This is actually more of a warning message, and for the purposes of RC extraction we can ignore this. Finally, we of course need to generate the real layout as a. This is what we will send to the foundry when we are ready to tapeout the chip. We can also use Cadence Innovus to do timing, area, and power analysis similar to what we did with Synopsys DC.

These post-place-and-route results will be much more accurate than the preliminary post-synthesis results. Note that for these results we used a target clock period of 0. This was the shortest clock period which still met timing without any negative slack during synthesis.

From the above report we can see that our design is still meeting timing even after place-and-route. Note that it is very likely that the critical path identified by Synsopsys DC after synthesis will not be the same critical path identified by Cadence Innovus after place-and-route. This is because Synopsys DC can only guess the final placement of the cells and interconnect during static timing analysis, while Cadence Innovus can use the real placement of the cells and interconnect during static timing analysis.

For the same reason, there is no guarantee that if your design meets timing after synthesis that it will still meet timing after place-and-route!